1. Field of the Invention
The present invention relates generally to techniques used to execute an instruction in a computer including a processor and a memory, and in particular to those implementing a desired program with a small program capacity and a small memory capacity.
2. Description of the Background Art
A computer system reads an instruction code from a storage circuit and causes a processor to decode the instruction code to execute an operation or the like. Computer systems are constantly required to provide rapid processing.
Japanese Patent Laying-Open No. 8-328817 discloses a computer system in which a main memory device is read less frequently to achieve rapid processing. This computer system includes a processor, a storage circuit storing therein an instruction code and data used by the processor, and a data expansion circuit expanding an instruction code and data read from the storage circuit to decompress the instruction code and data. The storage circuit stores the instruction code and data therein, compressed.
The storage circuit stores an instruction code and data compressed by a Huffman coding process or any other similar compression process. The data expansion circuit stores a code conversion table correlating an instruction code free of compression with the instruction code that is compressed, one for one. When the processor executes a fetch operation, a compressed instruction code is read from the storage circuit. In accordance with a compressed instruction and the code conversion table, the data expansion circuit recovers from a compressed instruction code a compression-free instruction code corresponding one for one to the instruction code. The processor receives the compression-free instruction code from the data expansion circuit and causes an instruction decoder to decode the instruction code to execute the instruction. The storage circuit thus has its compressed and stored instruction code and data expanded and thus decompressed to be an instruction code and data free of compression and thus provided to the processor. From the storage circuit a compressed instruction code can be read and a larger number of instruction codes can be read at one time. As such, if the storage circuit is read at low rates, a single instruction code can still be read faster than conventional to provide increased overall processing rate. Furthermore, compression and resultant, reduced program capacity allow the storage circuit to have reduced capacity for storing the program. As such, as compared to a case without compression, an equivalent function can be implemented with reduced system cost.
In the computer system of the above-described publication, however, the code conversion table is stored to correlate an instruction code free of compression with the instruction code that is compressed, one for one. For example if there are 100 instruction codes then in the code conversion table there are 100 entries and 100 compression-free instruction codes are thus stored in the table. This computer system is disadvantageous as it requires increased memory capacity to store this code conversion table.